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LSIs for MD Recorder
MN66621BRG
MD Record/Playback IC with ATRAC3 Support
s Overview
The MN66621BRG MD Record/Playback IC integrates functions of ATRAC encoding and decoding processing, sampling frequency conversion, digital servo, digital signal-processing, and memory controller on a single chip. A full-functionality MD player/recorder can be implemented by combining the MN66621BRG with an RF IC (the Panasonic AN22011A), DRAM, A/D and D/A converters, and a microcontroller.
s Features
ATRAC Compression/Expansion Functions * MDLP encoding/decoding support (LP2/LP4) * ATRAC encoding/decoding support (stereo and mono) * High-speed recording support (4x speed for all of the ATRAC, LP2, and LP4 modes) * High-fidelity encoding algorithms (ATRAC/LP2/LP4) * Uses a 24-bit digital signal processor (DSP) * Digital volume control with 10-bit smooth fade function (Playback: - dB to +18 dB, common left and right setting. Record: - dB to +18 dB, independent left and right settings.) * Peak level detection function * Silent segment detection function * Bass and treble boost functions * Low headphone sound leakage position (ASC) * Digital audio interface (IEC 958 conformant) * On-chip CD IC interface (audio and subcode data) Sampling Frequency Converter Function * Supported frequencies: 32 kHz, 44.1 kHz, 48 kHz Digital Signal-Processing Functions * ACIRC error correction (C1: double correction, C2: quadruple correction) * C1 error flag detection function Audio D/A Converter * On-chip audio D/A converter system, including a low-pass filter Memory Controller * Supported external DRAM organizations: 1 Mbit, 1 Mbit x 2, 4 Mbits, 4 Mbits x 2, 16 Mbits, 16 Mbits x 2, 64 Mbits. * The microcontroller can access external DRAM (The capacity used can be set under program control.) (Example) If the microcontroller uses 2 KB as a work area plus the area for 9 UTOC sectors in the external DRAM, the amount of data area available for shock prevention memory (SPM) will be as follows. Assuming one 4 Mbit DRAM is used: 4 Mbit is 1 024 x 1 024 x 4 = 4 194 304 bits Converting to bytes gives: 4 194 304/8 = 524 288 bytes Working area of 2 KB: 1 024 x 2 = 2 048 bytes Since 1 UTOC sector is 2 344 bytes, 9 sectors is: 2 344 x 9 = 21 096 bytes The remaining area after subtracting work area and UTOC area will be: 524 288 - 2 048 -21 096 = 510 144 bytes Dividing the remaining memory by the number of bytes in a sector (2 344 bytes) gives: 501 144/2 344 = 213.8 -> 213 sectors Similar calculations give: 46 sectors/1 Mbit, 101 sectors/2 Mbits, 884 sectors/16 Mbits, 3 568 sectors/64 Mbits
Publication date: Feburuary 2002
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MN66621BRG
s Features (continued)
Memory Controller (continued) * Simple TOC/UTOC editing commands * TOC/UTOC playback functions during recording Digital Servo * Focus, tracking, traverse, and spindle (EFM/ADIP/FG) servos Note that the FG servo system only applies when a stepping motor is used. * The traverse servo system supports both stepping and DC motors. * Supports three types of PWM output as servo outputs. * Status detection function: TRCRS, OFTR, BDO, NTJ, NRFDET, FLOCK, TLOCK, and SLOCK outputs provid * Bit detection function
s Applications
* MD players and MD recorders
RFSWHL RFSWPG DRVSEL [TVDM] 15 [TVDP] 16
20 19 DIGITAL SERVO PROCESSOR 18 STEPPER DRIVER 17 16 15 FM DEMODULATOR ADIP DECODER DIN PLL DSL SW EFM PLL EFM/ACIRC MODULATOR/ DEMODULATOR DIGITAL AUDIO INTERFACE CD LSI INTERFACE (AUDIO) CD LSI INTERFACE (SUBCODE) 70 33 32 SELECTER 31 25 24 23 20 SAMPLING RATE CONVERTER 19 18 17 92 93 94 38 37 36 MICROCONTROLLER INTERFACE CLOCK GENELATOR MASTER PLL SHOCK PROOF MEMORY CONTROLLER PWM GEN. AUDIO DAC MONITOR CONTROLLER EXTERNAL DRAM INTERFACE 30 ATRAC/ATRAC3 ENCODER/DECODER ADC/DAC INTERFACE 29 28 27 26 49 48
FODM
TRDM 11
LDON
SPDM
NREC
s Block Diagram
(FG)
FODP
3
4
5
7
8
23
14
21
22
9
10
AA BB CC DD FF1 FF2 VREFI MON3T OSC BTOM PEAK PEFMS PEFM1 EFMFIL EFMPLLF EFMIREF REFM RAD11 to RAD0 RDT3 to RDT0 NRAS NCAS NWE SCTSY MDISY SGSYNC
63 62 61 60 58 57 56 55 54 53 52 65 66 67 68 69 6 ADC
PWM GENERATOR (STPI2) (STPI1) (STPI0) (STPO2) (STPO1) (STPO0) ADIP TX RX1 RX2 LRCK BCK [DATA] [NCLDCK] [BLKCK] [SUBC] [SBCK] SCL SWS SDAP SDAR FS384 ADACL ADACR
42
39
41
46
40
97
98
72
43
12 MONI1
44 MONI2
TRDP
CLV2
SPDP
XI
SELAD
SSDW
APCD
NRST
SSCK
SSDR
XO
MONI0
Note) The MN66621BRG allows either a stepping motor or a DC motor to be selected for the sled system. Items in parentheses "( )" apply when a stepping motor is used, and items in square brackets "[ ]" apply when a DC motor is used.
2
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MONI3
45
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MN66621BRG
s Pin Arrangement
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
RAD9 RAD10 RAD11 MONI0 AVDD1 ADIP EFMIREF EFMPLLF EFMFIL PEFM1 PEFMS AVSS1 AA BB CC DD AVDD0 FF1 FF2 VREFI MON3T OSC BTOM PEAK AVSS0
RAD8 RAD7 RAD6 DVSS2 RAD5 RAD4 RAD3 RAD2 RAD1 DVDD2 RAD0 RDT3 IVDD1 RDT2 RDT1 RDT0 NRAS NCAS NWE TS2 DVSS0 XO XI IVDD0 TS1
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
ADACVDD ADACL ADACR ADACVSS NRST MONI3 MONI2 MONI1 SELAD SSCK SSDW SSDR SCTSY MDISY SGSYNC DVSS1 DVDD1 TX RX1 RX2 SCL SWS SDAP SDAR FS384
TS0 APCD RFSWPG RFSWHL CLV2 REFM SPDM SPDP FODM FODP TRDM TRDP DVDD0 LDON TVDM/STPO0 TVDP/STPO1 SBCK/STPO2 SUBC/STPI0 BLKCK/STPI1 NCLDCK/STPI2 NREC DRVSEL DATA/FG BCK LRCK
(TOP VIEW)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
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MN66621BRG
s Pin Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Pin Name TS0 APCD RFSWPG RFSWHL CLV2 REFM SPDM SPDP FODM FODP TRDM TRDP DVDD0 LDON TVDM/STPO0 TVDP/STPO1 SBCK/STPO2 SUBC/STPI0 BLKCK/STPI1 NCLDCK/STPI2 NREC DRVSEL DATA/FG BCK LRCK FS384 SDAR SDAP SWS SCL RX2 RX1 TX DVDD1 I/O DI DO DO DO DO DTO DTO DTO DTO DTO DTO DTO DVDD DO DTO DTO DO DI DI DI DO DSI DSI DI DI DO DI DO DO DO DI DI DO DVDD Test mode control input 0 Laser power setting PWM output Pit/groove setting signal High/low reflectivity setting signal Linear velocity switching signal EFM signal output Spindle minus side drive signal Spindle plus side drive signal Focus minus side drive signal Focus plus side drive signal Tracking minus side drive signal Tracking plus side drive signal Digital system power supply 0 Laser diode on/off control signal Traverse minus side drive signal, stepper drive signal 0 Traverse plus side drive signal, stepper drive signal 1 Subcode Q register clock output, stepper drive signal 2 Subcode Q code input, stepper status input 0 Subcode block clock signal input, stepper status input 1 Subcode frame clock signal input, stepper status input 2 Record/playback switching signal output Driver mode selection input CD input audio data, FG input CD input bit clock CD input word clock External A/D and D/A converter reference clock Audio data input Audio data output Word clock output Bit clock output Digital audio interface input 2 Digital audio interface input 1 Digital audio interface output Digital system power supply 1 Description
Note) I/O column notation DI: Digital input pin, DO: Digital output pin, DIO: Digital I/O pin, DSI: Digital I/O pin with Schmitt trigger circuit, DTO: Tristate digital output pin, AI: Analog input pin, AO: Analog output pin
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MN66621BRG
s Pin Descriptions (continued)
Pin No. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Pin Name DVSS1 SGSYNC MDISY SCTSY SSDR SSDW SSCK SELAD MONI1 MONI2 MONI3 NRST ADACVSS ADACR ADACL ADACVDD AVSS0 PEAK BTOM OSC MON3T VREFI FF2 FF1 AVDD0 DD CC BB AA AVSS1 PEFMS PEFM1 EFMFIL EFMPLLF I/O DVSS DO DO DO DO DSI DSI DSI DO DO DO DSI AVSS AO AO AVDD AVSS AI AI AI AI AI AI AI AVDD AI AI AI AI AVSS AI AO AO AO Digital system ground 1 ATRAC processing frame sync signal Microcontroller interrupt signal 1 Microcontroller interrupt signal 2 Read data (microcontroller interface) Write data (microcontroller interface) Shift clock (microcontroller interface) Address signal selection signal (microcontroller interface) Monitor output 1 Monitor output 2 Monitor output 3 Reset signal input Audio D/A converter ground Audio output: right channel Audio output: left channel Audio D/A converter power supply Analog system ground 0 Servo A/D converter input signal Servo A/D converter input signal Servo A/D converter input signal Servo A/D converter input signal Center point voltage input (reference voltage) Servo A/D converter input signal Servo A/D converter input signal Analog system ground 0 Servo A/D converter input signal Servo A/D converter input signal Servo A/D converter input signal Servo A/D converter input signal Analog system ground 1 EFM signal input EFM data slicing loop filter pin 1 EFM data slicing loop filter pin 2 EFM PLL filter pin Description
Note) I/O column notation DI: Digital input pin, DO: Digital output pin, DIO: Digital I/O pin, DSI: Digital I/O pin with Schmitt trigger circuit, DTO: Tristate digital output pin, AI: Analog input pin, AO: Analog output pin
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MN66621BRG
s Pin Descriptions (continued)
Pin No. 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pin Name EFMIREF ADIP AVDD1 MONI0 RAD11 RAD10 RAD9 RAD8 RAD7 RAD6 DVSS2 RAD5 RAD4 RAD3 RAD2 RAD1 DVDD2 RAD0 RDT3 IVDD1 RDT2 RDT1 RDT0 NRAS NCAS NWE TS2 DVSS0 XO XI IVDD0 TS1 I/O AI AI AVDD DO DO DO DO DO DO DO DVSS DO DO DO DO DO DVDD DO DIO IVDD DIO DIO DIO DO DO DO DI DVSS DO DI IVDD DI Description EFM PLL reference current setting pin ADIP signal input Analog system power supply 1 Monitor output 0 DRAM address output 11 DRAM address output 10 DRAM address output 9 DRAM address output 8 DRAM address output 7 DRAM address output 6 Digital system ground 2 DRAM address output 5 DRAM address output 4 DRAM address output 3 DRAM address output 2 DRAM address output 1 Digial system power supply 2 DRAM address output 0 DRAM data I/O 3 I/O system power supply 1 DRAM data I/O 2 DRAM data I/O 1 DRAM data I/O 0 DRAM RAS signal DRAM CAS signal DRAM write enable signal Test mode control input 2 Digital system ground 0 Crystal oscillator output Crystal oscillator input I/O system power supply 0 Test mode control input 1
Note) I/O column notation DI: Digital input pin, DO: Digital output pin, DIO: Digital I/O pin, DSI: Digital I/O pin with Schmitt trigger circuit, DTO: Tristate digital output pin, AI: Analog input pin, AO: Analog output pin
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MN66621BRG
s Electrical Characteristics
1. Absolute Maximum Ratings at VSS = AVSS = 0 V Item I/O digital system supply voltage Internal digital system supply voltage Analog system supply voltage Digital input pin voltage Digital output pin voltage Analog input pin voltage Analog output pin voltage Output current (HL4 type pins) Output current (HL8 type pins) Power dissipation Operating temperature Storage temperature Symbol IVDD DVDD AVDD VI VO VIA VOA IO IO PD Topr Tstg Rating - 0.3 to +4.6 - 0.3 to +2.5 - 0.3 to +4.6 - 0.3 to IVDD+0.3 (Maximum: 4.6) - 0.3 to IVDD+0.3 (Maximum: 4.6) - 0.3 to AVDD+0.3 (Maximum: 4.6) - 0.3 to AVDD+0.3 (Maximum: 4.6) 12 24 700 -10 to +70 -55 to +125 Unit V V V V V V V mA mA mW C C
Note) 1. The absolute maximum ratings are limit values for stresses applied to the chip so that the chip will not be destroyed. Operation is not guaranteed within these ranges. 2. All of the IVDD, DVDD, AVDD, VSS, and AVSS pins must be connected externally and the corresponding power or ground level supplied. 3. Insert bypass capacitors between the IVDD and VSS pins, the DVDD and VSS pins, and the AVDD and VSS pins. 4. Connect the TS0 to TS3 pins to VSS. 5. IVDD pins: IVDD0, IVDD1 DVDD pins: DVDD0, DVV1, DVDD2 AVDD pins: AVDD0, AVDD1, ADACVDD VSS pins: DVSS0, DVSS1, DVSS2 AVSS pins: AVSS0, AVSS1, ADACVSS Analog input pins: PEAK, BTOM, OSC, MON3T, VREFI, FF2, FF1, DD, CC, BB, AA, PEFMS, EFMIREF, ADIP Analog output pins: ADACL, ADACR, PEMF1, EFMFIL, EFMPLLF HL4 type pins: APCD, RFSWPG, RFSWHL, CLV2, REFM, SPDM, SPDP, FODM, FODP, TRDM, TRDP, LDON, TVDM, TVDP, SBCK, NREC, SDAP, SWS, SCL, TX, SGSYNC, MIDSY, SCTSY, SSDR, MONI1, MONI2, MONI3, MONI0, NWE HL8 type pins: FS384, RAD11 to RAD0, RDT3 to RDT0, NRAS, NCAS
2. Recommended Operating Conditions at VSS = AVSS = 0 V Item Symbol Condition Min Typ Max Unit 1) During normal speed operation I/O digital system supply voltage Internal digital system supply voltage Analog system supply voltage Ambient temperature Oscillator frequency IVDD DVDD AVDD Ta fosc Xtal : 16.9344 MHz
Note)
2.1 1.30 2.1 -10
3.3 1.8 3.3 16.9344
3.6 1.95 3.6 70
V V V C MHz
XI
XO
Appropriate values of these circuit constants depend on the type of the oscillator element used. Consult the manufacturer of the oscillator element to determine appropriate values for the element used.
CXI
CXO
Figure 1. Oscillator circuit example
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MN66621BRG
s Electrical Characteristics (continued)
2. Recommended Operating Conditions (continued) at VSS = AVSS = 0 V Item Symbol Condition Min Typ Max Unit 2) During high speed operation (2x to 4x ATRAC, 2x to 4x ATRAC3) I/O digital system supply voltage Internal digital system supply voltage Analog system supply voltage Ambient temperature Oscillator frequency IVDD DVDD AVDD Ta fosc Xtal : 16.9344 MHz 3.0 1.65 3.0 -10 3.3 1.8 3.3 16.9344 3.6 1.95 3.6 70 V V V C MHz
Note) This IC cannot be used in self-oscillation mode at 33.8688 MHz (768Fs). For that frequency, input a clock signal directly to the XI pin.
3. DC Characteristics at IVDD = 2.1 V to 3.6 V, AVDD = 2.1 V to 3.6 V, DVDD = 1.30 V to 1.95 V, VSS = AVSS = 0 V, Ta = -10C to 70C Item Supply current (normal speed) DVDD supply IVDD supply AVDD supply Symbol IDD IDDI IDDA Condition IVDD = AVDD = 3.3 V DVDD = 1.80 V VI = IVDD or VSS f = 16.9344 MHz, no load Supply current (standby mode) DVDD supply IVDD supply AVDD supply 1) Oscillator circuit: XI, XO High-level input voltage Low-level input voltage Internal feedback resistor VIH VIL RFB VIH VIL ILI VIH VIL RIL ILI VI = IVDD VI = VSS IVDD = 3.3 V IVDD x 0.8 0 0.33 1 30 IVDD IVDD x 0.2 3 V V M IDD IDDI IDDA VI = IVDD or VSS No load, with the clock stopped DVDD = 1.5 V 8 3.5 1 mA Min Typ 20 6 6.5 Max 40 12 13 Unit mA
2) CMOS input level pins: TS0, TS1, RX1, RX2, SDAR, LRCK, BCK, DATA, DRVSEL, NCLDCK, BLKCK, SUBC High-level input voltage Low-level input voltage Input leakage current IVDD x 0.8 0 IVDD IVDD x 0.2 10 V V A
3) CMOS input level pins with built-in pull-down resistors: TS2 High-level input voltage Low-level input voltage Pull-down resistor Input leakage current IVDD x 0.8 0 8 IVDD IVDD x 0.2 100 10 V V k A
8
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MN66621BRG
s Electrical Characteristics (continued)
3. DC Characteristics (continued) IVDD = 2.1 V to 3.6 V, AVDD = 2.1 V to 3.6 V, DVDD = 1.30 V to 1.95 V, VSS = AVSS = 0 V, Ta = -10C to 70C Item Symbol Condition Min Typ Max Unit 4) CMOS input level pins with built-in Schmitt trigger circuit: NRST, SSCK, SSDW, SELAD High-level input voltage Low-level input voltage Input leakage current 5) Push-pull outputs - HL4 type: High-level output voltage Low-level output voltage VIH VIL ILI VI = IVDD or VSS IVDD x 0.8 0 IVDD IVDD x 0.2 10 V V A
APCD, RFSWPG, RFSWHL, CLV2, LDON, SBCK, NREC, SDAP, SWS, SCL, TX, SGSYNC, MDISY, SCTSY, SSDR, MONI1, MONI2, MONI3, MONI0, NWE VOH VOL IOH = -2.0 mA VI = IVDD or VSS IOL = 2.0 mA VI = IVDD or VSS IOH = -4.0 mA VI = IVDD or VSS IOL = 4.0 mA VI = IVDD or VSS IVDD - 0.5 0.5 V V
6) Push-pull outputs - HL4 type: FS384, RAD11 to RAD0, NRAS, NCAS High-level output voltage Low-level output voltage VOH VOL IVDD - 0.5 0.5 V V
7) CMOS level I/O pins - HL8 type: RDT3 to RDT0 High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Output leakage current VIH VIL VOH VOL OLI VOH VOL OLI IOH = -4.0 mA VI = IVDD or VSS IOL = 4.0 mA VI = IVDD or VSS VI = IVDD or VSS IOH = -2.0 mA VI = IVDD or VSS IOL = 2.0 mA VI = IVDD or VSS VI = IVDD or VSS IVDD x 0.8 0 IVDD - 0.5 IVDD IVDD x 0.2 0.5 10 0.5 10 V V V V A
8) Push-pull tristate outputs - HL4 type: TVDP, TRDT, FODP, SPDP, REFM, TVDM, TRDM, FODM, SPDM High-level output voltage Low-level output voltage Output leakage current IVDD - 0.5 V V A
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MN66621BRG
s Application Circuit Example
Driver IC
DIGITAL IN1 DIGITAL IN2 DIGITAL OUT
22 k 22 k
RX1 RX2 TX
SPDM SPDP FODM FODP TRDM TRDP TVDM TVDP
APCREF RF IC * (AN22011A) NREC AA BB CC DD FF1 FF2 MON3T PEAK BOTM OUTRF
0.001 F 1 000pF 1 000pF
APCD MN66621BRG NREC AA BB CC DD FF1 FF2 MON3T PEAK BOTM PEFMS
0.022 F
SELAD SSCK SSDW SSDR SGSYNC MDISY SCTSY NRST SCL SWS FS384 SDAP SDAR
Microcontroller
A/D and D/A converters
RAD0 to RAD11 RDT0 to RDT3 NRAS NCAS NWE LRCK BCK DATA SUBC BLCK NCLDCK SBCK MONI0 MONI1 MONI2 MONI3 REFM ADACL ADACR OSC
DRAM
Audio data CD LSI
Subcode data *
PEFM1 EFMFIL
33 k 33 k
VREF ADIP RFSWPG RFSWHL CLV2 LDON
0.1 F
IREFI ADIP RFSWPG RFSWHL
N.C. N.C. N.C. N.C. Magnetic head driver Amplifier
VREF 12 k AVDD
TS0 to TS2
CLV2 LDON
DRVSEL
EFMIREF EFMPLLF
XI
XO
220 0.022 F 680 pF
16.9344 MHz
Note) *: This device assumes the use of Panasonic AN22011A as RF IC, and Panasonic MN662790 (or similar products) as subcode interface.
10
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MN66621BRG
s Package Dimensions (Unit: mm)
* TQFP100-P 1414E (Lead-free package)
16.000.20 14.000.10 75 76 51 50 (1.00) 14.000.10 100 1 (1.00) 0.50 0.18+0.10 -0.05 1.20 max. 0.10 M (1.00) (1.00)
0.150.05
26 25
0.10+0.10 -0.05
16.000.20
0 to 8 0.500.10
0.10
Seating plane
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Request for your special attention and precautions in using the technical information and semiconductors described in this material
(1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. (2) The technical information described in this material is limited to showing representative characteristics and applied circuit examples of the products. It does not constitute the warranting of industrial property, the granting of relative rights, or the granting of any license. (3) The products described in this material are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: * Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. * Any applications other than the standard applications intended. (4) The products and product specifications described in this material are subject to change without notice for reasons of modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (5) When designing your equipment, comply with the guaranteed values, in particular those of maximum rating, the range of operating power supply voltage and heat radiation characteristics. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, redundant design is recommended, so that such equipment may not violate relevant laws or regulations because of the function of our products. (6) When using products for which dry packing is required, observe the conditions (including shelf life and after-unpacking standby time) agreed upon when specification sheets are individually exchanged. (7) No part of this material may be reprinted or reproduced by any means without written permission from our company.
Please read the following notes before using the datasheets
A. These materials are intended as a reference to assist customers with the selection of Panasonic semiconductor products best suited to their applications. Due to modification or other reasons, any information contained in this material, such as available product types, technical data, and so on, is subject to change without notice. Customers are advised to contact our semiconductor sales office and obtain the latest information before starting precise technical research and/or purchasing activities. B. Panasonic is endeavoring to continually improve the quality and reliability of these materials but there is always the possibility that further rectifications will be required in the future. Therefore, Panasonic will not assume any liability for any damages arising from any errors etc. that may appear in this material. C. These materials are solely intended for a customer's individual use. Therefore, without the prior written approval of Panasonic, any other use such as reproducing, selling, or distributing this material to a third party, via the Internet or in any other way, is prohibited.
2001 MAR
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